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Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Electronics and Communication Engineering | - |
dc.date.accessioned | 2022-09-09T06:07:49Z | - |
dc.date.available | 2022-09-09T06:07:49Z | - |
dc.date.issued | 2022-08 | - |
dc.identifier.uri | http://hdl.handle.net/123456789/4257 | - |
dc.language.iso | en | en_US |
dc.publisher | PESCE | en_US |
dc.subject | System Verilog (Technical Skills - I) | en_US |
dc.title | System Verilog (Technical Skills - I) | en_US |
dc.type | Learning Object | en_US |
Appears in Collections: | 3rd Year |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
P18EC592-U1.pdf | 89.35 kB | Adobe PDF | View/Open |
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